A PLL can be regarded as a feedback circuit system that compares to an inputted phase with a feedback phase to adjust a outputted phase, i.e., the PLL used in a transmitter is inputted with a low-frequency (LF) periodic signal to output a high-frequency (HF) periodic signal, with a certain constant phase relationship between the inputted signal and the outputted signal. The PLL mainly comprises a phase frequency detector (PFD), a charge pump, a loop filter and a voltage controlled oscillator (VCO). In practice, the PLL is widely applied to electronic and communication products, e.g., memories, microprocessors, hard disk driving apparatuses, radio frequency (RF) transceivers, and fiber optic transceivers.
FIG. 1 shows a block diagram of a conventional PLL. A PLL 1 comprises a phase frequency detector (PFD) 10, a charge pump 12, a loop filter 14, a voltage controlled oscillator (VCO) 16 and a frequency divider 18. The charge pump 12 is coupled between the PFD 10 and the loop filter 14, the loop filter 14 is coupled to the VCO 16, and the frequency divider 18 is coupled between the PFD 10 and the VCO 16.
Upon receiving a reference clock CKR and a feedback clock CKV, the PFD 10 compares the reference clock CKR with the feedback clock CKV to generate a phase difference ΔΦ that is transmitted to the charge pump 12. The feedback clock CKV is generated by the frequency divider 18 from frequency dividing an output frequency fout of the VCO 16 with a predetermined divisor. According to the phase difference ΔΦ, the charge pump 12 generates a corresponding charge pump current I that is outputted to the loop filter 14. Upon receiving the charge pump current I, the loop filter 14 converts the charge pump current I into a control voltage V via its impedance, and outputs the control voltage V to the VCO 16. After that, the VCO 16 generates a corresponding output frequency fout according to the control voltage V.
The loop filter 14 is one of most critical components of the PLL 1. Considering cost and efficiency, the PLL 1 is commonly realized by a second-order low-pass filter composed of resistors and capacitors. Generally speaking, the PLL 14 has several important parameters, e.g., phase margin, loop bandwidth, and loop filter topology, and the loop bandwidth needed for eliminating noises and determining a locking time is the most critical parameter.
When the loop frequency of the loop filter 14 is small, although the loop filter 14 can effectively eliminate noises created by inputting the reference frequency and switching the charge pump 12 as well as reducing undesirable effects caused by jitter, a disadvantage that the loop filter 14 requires a long locking time is incurred since the locking time is directly proportional to the loop bandwidth. On the contrary, when the loop bandwidth of the loop filter 14 is enlarged, the locking time is reduced; nevertheless, the PLL 14 can not restrain the foregoing noises.
Therefore, one object of the present disclosure is to provide a loop bandwidth control apparatus applied to a PLL and a method thereof to solve the foregoing problem.